Details
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Type:
Story
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Status: Done
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Resolution: Done
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Fix Version/s: None
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Component/s: ip_diffim, pipe_tasks
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Labels:
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Story Points:10
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Epic Link:
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Sprint:AP F18-4
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Team:Alert Production
Description
Frequency regularization in dcrAssembleCoadd.py is designed to suppress positive/negative sidelobes around bright sources, while not zeroing-out the noise. However, the sidelobe suppression leaves some sidelobes in place that I would naively expect to be reduced. These residual sidelobes may be affecting source measurement, and the regularization should be improved.
Please note that this ticket also includes a pull request for pipe_tasks, which no longer shows up in Jira.