Fix the interlock signal on M2 cell. It looks like the bit value of interlock is decided by the high-level business logic (the vi execution has the problem or not) instead of reading the value from the cRIO.

The following figure is the connection of interlock:

Look at the connection diagram, there’s 2 signals connected from Pilz to the cRIO1:

 - X3-13 is the power for the actuators relay, so this should be "Interlock Power Relay On".  So this signal could be be always on (as is the Pilz which finally control the pass to the relay).

 - X4-Y32 is the indicator the interlock is engaged or not, so this should be " Interlock Enable ".  This signal should change when the interlock is engaged (should be ‘’0’’ when the Estop is pressed).
 

Other clarification from Franco:

Regarding the interlocks connections:
(a) When the Estop is not engaged, you should see a logic ''1'' on the inputs slot4-input5 and slot 5-input37 on cRIO
(b) When the Estop is pressed (and no being reset), you still should see a ''1'' on the input5 of slot4, but now you should see a ''0'' on the input 37 of slot5

Sorry, input 5 of slot4 is an output actually (its the 24V signal for powering the actuators) and input 37 slot 5 is the same signal after the Pilz relay...so if the interlock is engaged, basically the Pilz relay interrupt the signal to arrive to the actuators.