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  1. Data Management
  2. DM-37451

Document interface for readDaq in ts_m2fpga project in Phase 4

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    • Type: Story
    • Status: Done
    • Resolution: Done
    • Fix Version/s: None
    • Component/s: ts_main_telescope
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      Description

      Continue the experiment with LabVIEW FPGA code and C programming using the FPGA C API Interface. Work on the comments/questions in the previous tickets DM-36940 and DM-37040.

      • question2: what will happen if I want to release 5 elements and there are only 2 or 0 elements in the FIFO?
      • question3: what will happen if I want to add more elements in the FIFO but there is no available space?

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          Story - Created by Jira Software - do not edit or delete. Issue type for a user story. DM-37040 Document interface for readDaq in ts_m2fpga project in Phase 3

          • Done
          is triggering

          Story - Created by Jira Software - do not edit or delete. Issue type for a user story. DM-37573 Document interface for readDaq in ts_m2fpga project in Phase 5

          • Done

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            pcortes Patricio Cortes added a comment - - edited

            Based on my experimentation with the scenario you described before, for the first iteration, there is no problem. But for the second iteration, we will get the Timed Out? terminal in True after 6 new elements were written in.

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            pcortes Patricio Cortes added a comment - - edited Based on my experimentation with the scenario you described before, for the first iteration, there is no problem. But for the second iteration, we will get the Timed Out? terminal in True after 6 new elements were written in.
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            pcortes Patricio Cortes added a comment - - edited

            Please check the first modified comment. I already answered the last question. 

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            pcortes Patricio Cortes added a comment - - edited Please check the first modified comment. I already answered the last question. 
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            ttsai Te-Wei Tsai added a comment -

            You are sure 6 elements were written in? How?

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            ttsai Te-Wei Tsai added a comment - You are sure 6 elements were written in? How?
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            ttsai Te-Wei Tsai added a comment -

            Because the "for" loop is used in the FPGA side, 6 elements will be written in.

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            ttsai Te-Wei Tsai added a comment - Because the "for" loop is used in the FPGA side, 6 elements will be written in.
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            ttsai Te-Wei Tsai added a comment -

            Great job done! Now we know the behavior of FIFO and C API.

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            ttsai Te-Wei Tsai added a comment - Great job done! Now we know the behavior of FIFO and C API.

              People

              Assignee:
              pcortes Patricio Cortes
              Reporter:
              pcortes Patricio Cortes
              Reviewers:
              Te-Wei Tsai
              Watchers:
              Patricio Cortes, Te-Wei Tsai
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